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Low Power, High Speed and Area Efficient Binary Count Multiplier.
Kore Sagar Dattatraya
Ritesh Belgudri
Ramdas Bhanudas Khaladkar
V. S. Kanchana Bhaaskaran
Published in:
J. Circuits Syst. Comput. (2016)
Keyphrases
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low power
high speed
low cost
power consumption
high power
single chip
wireless transmission
low power consumption
vlsi architecture
image sensor
real time
digital signal processing
highly efficient
mixed signal
logic circuits
frame rate
gate array
power reduction
cmos technology
floating point
motion estimation