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Bhuvana B. P.
ORCID
Publication Activity (10 Years)
Years Active: 2018-2020
Publications (10 Years): 5
Top Topics
Positive Feedback
Low Power Consumption
Flip Flops
Low Power
Top Venues
iSES
Microelectron. J.
VLSI Design
J. Circuits Syst. Comput.
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Publications
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Bhuvana B. P.
,
V. S. Kanchana Bhaaskaran
Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures.
J. Circuits Syst. Comput.
29 (1) (2020)
E. Ramkumar
,
D. Gracin
,
P. Rajkamal
,
Bhuvana B. P.
,
V. S. Kanchana Bhaaskaran
Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS).
iSES
(2020)
Bhuvana B. P.
,
V. S. Kanchana Bhaaskaran
Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications.
Microelectron. J.
92 (2019)
Jayashree K. G
,
Lois Priscilla S
,
Bhuvana B. P.
,
Kanchana Bhaaskaran V. S
Design and Analysis of FinFET Based CSCPAL Low Power Adder.
iSES
(2019)
Bhuvana B. P.
,
V. S. Kanchana Bhaaskaran
Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack.
VLSI Design
(2018)