Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS).
E. RamkumarD. GracinP. RajkamalBhuvana B. P.V. S. Kanchana BhaaskaranPublished in: iSES (2020)
Keyphrases
- low power
- high speed
- logic circuits
- power dissipation
- power consumption
- single chip
- cmos technology
- gate array
- low cost
- low power consumption
- vlsi architecture
- power reduction
- mixed signal
- wireless transmission
- digital signal processing
- frame rate
- circuit design
- design methodology
- high power
- vlsi circuits
- nm technology
- real time