Differential Cascode Adiabatic Logic Structure for Low Power.

V. S. Kanchana Bhaaskaran J. P. Raina

Published in: J. Low Power Electron. (2008)

Keyphrases

low power
high speed
power consumption
logic circuits
low cost
delay insensitive
digital signal processing
high power
single chip
vlsi architecture
low power consumption
wireless transmission
computer simulation
gate array
power dissipation
power reduction