Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit.
A. Anita AngelineV. S. Kanchana BhaaskaranPublished in: IET Circuits Devices Syst. (2019)
Keyphrases
- high speed
- low power
- circuit design
- power dissipation
- logic circuits
- chip design
- software architecture
- computer aided
- engineering design
- cmos technology
- high speed networks
- phase locked loop
- information systems
- shift register
- power reduction
- electronic circuits
- power consumption
- design process
- building blocks
- software engineering
- case study