Low power vedic multiplier using energy recovery logic.
Hardik SanganiTanay M. ModiV. S. Kanchana BhaaskaranPublished in: ICACCI (2014)
Keyphrases
- low power
- logic circuits
- power consumption
- energy dissipation
- energy efficiency
- low cost
- high speed
- delay insensitive
- ultra low power
- energy saving
- digital signal processing
- single chip
- wireless transmission
- high power
- low power consumption
- power dissipation
- cmos technology
- image sensor
- energy consumption
- power saving
- gate array
- vlsi architecture
- mixed signal
- hardware and software
- multi channel
- vlsi circuits
- real time