Tiantao Lu

Publication Activity (10 Years)

Years Active: 2013-2019
Publications (10 Years): 8

Top Topics

Driven Learning

Multicore Processors

Vlsi Architecture

Error Reduction

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Zhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava
Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (11) (2019)
Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Sandeep Kumar Samal, Sung Kyu Lim, Ankur Srivastava
TSV-Based 3-D ICs: Design Methods and Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (10) (2017)
Zhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava
Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors. DAC (2017)
Tiantao Lu, Ankur Srivastava
Low-Power Clock Tree Synthesis for 3D-ICs. ACM Trans. Design Autom. Electr. Syst. 22 (3) (2017)
Tiantao Lu, Zhiyuan Yang, Ankur Srivastava
Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction. ISVLSI (2016)
Tiantao Lu, Zhiyuan Yang, Ankur Srivastava
Electromigration-aware placement for 3D-ICs. ISQED (2016)
Yang Xie, Chongxi Bao, Caleb Serafy, Tiantao Lu, Ankur Srivastava, Mark M. Tehranipoor
Security and Vulnerability Implications of 3D ICs. IEEE Trans. Multi Scale Comput. Syst. 2 (2) (2016)
Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Ankur Srivastava
Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs. ISLPED (2016)
Tiantao Lu, Ankur Srivastava
Modeling and Layout Optimization for Tapered TSVs. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Tiantao Lu, Ankur Srivastava
Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs. ACM Great Lakes Symposium on VLSI (2015)
Tiantao Lu, Ankur Srivastava
Gated low-power clock tree synthesis for 3D-ICs. ISLPED (2014)
Tiantao Lu, Ankur Srivastava
Detailed electrical and reliability study of tapered TSVs. 3DIC (2013)