Syed Mohsin Abbas

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 21

Top Topics

Belief Propagation

Rayleigh Fading

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

GLOBECOM (Workshops)

Publications

Syed Mohsin Abbas, Chi-Ying Tsui, Marwan Jalaleddine, Warren J. Gross
Step-GRAND: A Low Latency Universal Soft-Input Decoder. GLOBECOM (Workshops) (2023)
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding. IEEE Trans. Very Large Scale Integr. Syst. 31 (1) (2023)
Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross
Step-GRAND: A Low Latency Universal Soft-input Decoder. CoRR (2023)
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND. IEEE Trans. Very Large Scale Integr. Syst. 30 (6) (2022)
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
GRAND for Rayleigh Fading Channels. CoRR (2022)
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
GRAND for Rayleigh Fading Channels. GLOBECOM (Workshops) (2022)
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO). J. Signal Process. Syst. 94 (10) (2022)
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
List-GRAND: A practical way to achieve Maximum Likelihood Decoding. CoRR (2021)
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND. CoRR (2021)
Jiajie Li, Syed Mohsin Abbas, Thibaud Tonnellier, Warren J. Gross
Reduced Complexity RPA Decoder for Reed-Muller Codes. ISTC (2021)
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND. CoRR (2021)
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross
High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND. ICASSP (2021)
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
High-Throughput VLSI Architecture for GRAND Markov Order. SiPS (2021)
Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross
High-Throughput VLSI Architecture for GRAND Markov Order. CoRR (2021)
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Warren J. Gross
High-Throughput VLSI Architecture for GRAND. CoRR (2020)
Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Warren J. Gross
High-Throughput VLSI Architecture for GRAND. SiPS (2020)
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
Concatenated LDPC-polar codes decoding through belief propagation. ISCAS (2017)
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
Concatenated LDPC-Polar Codes Decoding Through Belief Propagation. CoRR (2017)
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Syed Mohsin Abbas, Chi-Ying Tsui
Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. VLSI-SoC (2016)
Syed Mohsin Abbas, Chi-Ying Tsui
Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO. VLSI-SoC (Selected Papers) (2016)
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
Low Complexity Belief Propagation Polar Code Decoders. CoRR (2015)
Syed Mohsin Abbas, YouZhe Fan, Ji Chen, Chi-Ying Tsui
Low complexity belief propagation polar code decoder. SiPS (2015)
Zhiliang Qian, Syed Mohsin Abbas, Chi-Ying Tsui
FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Syed Mohsin Abbas, Soonyoung Lee, Sanghyeon Baeg, Sungju Park
An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory. IEEE Trans. Computers 63 (8) (2014)