Sasindu Wijeratne

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 26

Top Topics

Hardware Architecture

Tensor Decomposition

Random Access Memory

Top Venues

Publications

Sasindu Wijeratne, Bingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart
PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images. CoRR (2024)
Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
Sparse MTTKRP Acceleration for Tensor Decomposition on GPU. CoRR (2024)
Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
Sparse MTTKRP Acceleration for Tensor Decomposition on GPU. CF (2024)
Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. SBAC-PAD (2023)
Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. CoRR (2023)
Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna
Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA. FPGA (2023)
Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna
Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. CoRR (2023)
Bingyi Zhang, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart
Graph Neural Network for Accurate and Low-complexity SAR ATR. CoRR (2023)
Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna
Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. FPL (2023)
Sasindu Wijeratne, Akhilesh R. Jaiswal, Ajey P. Jacob, Bingyi Zhang, Viktor K. Prasanna
Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA. HPEC (2022)
Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna
Towards Programmable Memory Controller for Tensor Decomposition. CoRR (2022)
Bingyi Zhang, Akhilesh R. Jaiswal, Clynn Mathew, Ravi Teja Lakkireddy, Ajey P. Jacob, Sasindu Wijeratne, Viktor K. Prasanna
Modeling the Energy Efficiency of GEMM using Optical Random Access Memory. HPEC (2022)
Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna
Towards Programmable Memory Controller for Tensor Decomposition. DATA (2022)
Sasindu Wijeratne, Akhilesh R. Jaiswal, Ajey P. Jacob, Bingyi Zhang, Viktor K. Prasanna
Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA. CoRR (2022)
Tian Ye, Sanmukh R. Kuppannagari, César A. F. De Rose, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
Estimating the Impact of Communication Schemes for Distributed Graph Processing. ISPDC (2022)
Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual
Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks. CoRR (2021)
Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor K. Prasanna
Programmable FPGA-based Memory Controller. HOTI (2021)
Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. HPEC (2021)
Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor K. Prasanna
Programmable FPGA-based Memory Controller. CoRR (2021)
Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. CoRR (2021)
Ruizhi Zhang, Sasindu Wijeratne, Yang Yang, Sanmukh R. Kuppannagari, Viktor K. Prasanna
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. CoRR (2021)
Ruizhi Zhang, Sasindu Wijeratne, Yang Yang, Sanmukh R. Kuppannagari, Viktor K. Prasanna
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. HPEC (2020)
Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. CoRR (2019)
Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. FPGA (2019)
Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual
Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks. ASAP (2018)
Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. ASAP (2017)