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Ashen Ekanayake
Publication Activity (10 Years)
Years Active: 2017-2024
Publications (10 Years): 7
Top Topics
Memory Access
Hardware Architectures
Xilinx Virtex
Systolic Array
Top Venues
CoRR
ASAP
J. Syst. Archit.
FPGA
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Publications
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Fernando Mosquera
,
Ashen Ekanayake
,
William Hua
,
Krishna Kavi
,
Gayatri Mehta
,
Lizy Kurian John
SecurityCloak: Protection against cache timing and speculative memory access attacks.
J. Syst. Archit.
150 (2024)
Qinzhe Wu
,
Ashen Ekanayake
,
Ruihao Li
,
Jonathan Beard
,
Lizy Kurian John
SPAMeR: Speculative Push for Anticipated Message Requests in Multi-Core Systems.
ICPP
(2022)
Qinzhe Wu
,
Jonathan Beard
,
Ashen Ekanayake
,
Andreas Gerstlauer
,
Lizy K. John
Virtual-Link: A Scalable Multi-Producer Multi-Consumer Message Queue Architecture for Cross-Core Communication.
IPDPS
(2021)
Qinzhe Wu
,
Jonathan Beard
,
Ashen Ekanayake
,
Andreas Gerstlauer
,
Lizy K. John
Virtual-Link: A Scalable Multi-Producer, Multi-Consumer Message Queue Architecture for Cross-Core Communication.
CoRR
(2020)
Sasindu Wijeratne
,
Ashen Ekanayake
,
Sandaruwan Jayaweera
,
Danuka Ravishan
,
Ajith Pasqual
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.
CoRR
(2019)
Sasindu Wijeratne
,
Ashen Ekanayake
,
Sandaruwan Jayaweera
,
Danuka Ravishan
,
Ajith Pasqual
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.
FPGA
(2019)
Rishan Senanayake
,
Namitha Liyanage
,
Sasindu Wijeratne
,
Sachille Atapattu
,
Kasun Athukorala
,
P. M. K. Tharaka
,
Geethan Karunaratne
,
R. M. A. U. Senarath
,
Ishantha Perera
,
Ashen Ekanayake
,
Ajith Pasqual
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension.
ASAP
(2017)