Ajith Pasqual

Publication Activity (10 Years)

Years Active: 1998-2022
Publications (10 Years): 16

Top Topics

Hardware Architectures

Top Venues

IEEE Trans. Circuits Syst. Video Technol.

Publications

Thilina S. Ambagahawaththa, Dulika Nayanasiri, Ajith Pasqual
A Four-Step Method to Synthesize a DC-DC Converter for Multi-Inductor Realizable Arbitrary Voltage Conversion Ratio. IEEE Trans. Ind. Electron. 69 (6) (2022)
Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual
Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks. CoRR (2021)
Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. CoRR (2019)
Nisal Ranasinghe, Ravindu Bangamuarachchi, Jayath Seneviratne, Achini Jayawardane, Ajith Pasqual, R. M. A. U. Senarath
SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks. ASAP (2019)
Kamlakannan Kamalavasan, Ratnasegar Natheesan, Kathirgamaraja Pradeep, Sivakumaran Gowthaman, Sivakaneshan Aravinth, Ajith Pasqual
FPGA IP for Real-time 4K HDR Image Decoding in VR Devices. LASCAS (2019)
Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. FPGA (2019)
Kathirgamaraja Pradeep, Kamalakkannan Kamalavasan, Ratnasegar Natheesan, Ajith Pasqual
EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA. ICECS (2018)
Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual
Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks. ASAP (2018)
Dakila Serasinghe, Duvindu Piyasena, Ajith Pasqual
A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform. DSD (2018)
Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. ASAP (2017)
Ayanga D. Kalupahana, Nisal Hemadasa, Nipun Wijerathne, Anuranga Ranasinghe, Ajith Pasqual
FPAA and FPGA based universal sensor node design. ICST (2017)
Kosala Perera, Udesh Gunarathne, Binal Chathuranga, Chamika Ramanayake, Ajith Pasqual
Hybrid Software Defined Networking Controller. DCNET (2017)
P. M. K. Tharaka, D. M. D. Wijerathne, Navoda Perera, Dinushan Vishwajith, Ajith Pasqual
Runtime rule-reconfigurable high throughput NIPS on FPGA. FPT (2017)
Viduranga Bandara Wijekoon, T. M. Dananjaya, P. H. Kariyawasam, S. Iddamalgoda, Ajith Pasqual
High performance flow matching architecture for OpenFlow data plane. NFV-SDN (2016)
Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera, Ajith Pasqual
Real time all intra HEVC HD encoder on FPGA. ASAP (2016)
Maleen Abeydeera, Manupa Karunaratne, Geethan Karunaratne, Kalana De Silva, Ajith Pasqual
4K Real-Time HEVC Decoder on an FPGA. IEEE Trans. Circuits Syst. Video Technol. 26 (1) (2016)
Maleen Abeydeera, Ajith Pasqual
HEVC inverse transform architecture utilizing coefficient sparsity. ICIP (2015)
Samoda Gamage, Ajith Pasqual
High performance parallel packet Classification architecture with Popular Rule Caching. ICON (2012)
Ravina Panangalage, Ajith Pasqual
Impact of ICT on learning and teaching. ISTAS (2008)
Ajith Pasqual, Hidenori Takeshima, Kiyoharu Aizawa
Software Based Object Tracking with Visual Feature Integration. ICIP (2) (1999)
Ajith Pasqual, Kiyoharu Aizawa, Mitsutoshi Hatori
Selection/Substitution of Visual Features for Object Tracking. MVA (1998)