Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks.
Sasindu WijeratneSandaruwan JayaweeraMahesh DananjayaAjith PasqualPublished in: CoRR (2021)
Keyphrases
- convolutional neural networks
- systolic array
- parallel architecture
- computation intensive
- hardware implementation
- instruction set
- convolutional network
- heterogeneous computing
- multi processor
- functional units
- digital signal
- management system
- low cost
- reconfigurable architecture
- parallel processing
- level parallelism
- data flow
- high precision
- general purpose processors
- precision and recall
- processing elements
- industry standard
- multi core processors
- high speed
- general purpose
- dynamic reconfiguration
- ibm zenterprise
- field programmable gate array
- numerical methods
- associative memory
- software architecture