Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA.
Sasindu WijeratneRajgopal KannanViktor K. PrasannaPublished in: HPEC (2021)
Keyphrases
- low latency
- high speed
- field programmable gate array
- hardware implementation
- low cost
- digital signal
- real time
- systolic array
- high throughput
- high bandwidth
- highly efficient
- reconfigurable hardware
- virtual machine
- massive scale
- stream processing
- high dimensional
- continuous query processing
- processing elements
- parallel computing
- embedded systems
- data acquisition
- main memory
- data analysis