Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA.
Sasindu WijeratneRajgopal KannanViktor K. PrasannaPublished in: CoRR (2021)
Keyphrases
- low latency
- high speed
- field programmable gate array
- hardware implementation
- real time
- low cost
- high bandwidth
- digital signal
- systolic array
- highly efficient
- high throughput
- reconfigurable hardware
- virtual machine
- stream processing
- massive scale
- embedded systems
- processing elements
- high dimensional
- parallel computing
- orders of magnitude
- distributed systems