Rafael Gadea Gironés

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 3

Top Topics

Benchmark Classification Problems

Evolutionary Optimization

Energy Efficiency

Top Venues

Microprocess. Microsystems

J. Supercomput.

Publications

Rafael Gadea Gironés, Jorge D. Fe, José María Monzó
Task parallelism-based architectures on FPGA to optimize the energy efficiency of AI at the edge. Microprocess. Microsystems 98 (2023)
Rafael Gadea Gironés, Ricardo José Colom-Palero, Vicente Herrero-Bosch
Optimization of Deep Neural Networks Using SoCs with OpenCL. Sensors 18 (5) (2018)
Jorge D. Fe, Ramón José Aliaga, Rafael Gadea Gironés
Evolutionary optimization of neural networks with heterogeneous computation: study and implementation. J. Supercomput. 71 (8) (2015)
Jorge D. Fe, Ramón José Aliaga, Rafael Gadea Gironés
Experimental Platform for Accelerate the Training of ANNs with Genetic Algorithm and Embedded System on FPGA. IWINAC (2) (2013)
Néstor Ferrando, M. A. Gosálvez, Joaquín Cerdá, Rafael Gadea Gironés, Kazuo Sato
Octree-based, GPU implementation of a continuous cellular automaton for the simulation of complex, evolving surfaces. Comput. Phys. Commun. 182 (3) (2011)
Fernando Mateo, Dusan Sovilj, Rafael Gadea Gironés
Approximate k-NN delta test minimization method using genetic algorithms: Application to time series. Neurocomputing 73 (10-12) (2010)
Fernando Mateo, Dusan Sovilj, Rafael Gadea Gironés, Amaury Lendasse
RCGA-S/RCGA-SP Methods to Minimize the Delta Test for Regression Tasks. IWANN (1) (2009)
Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá, Néstor Ferrando, Vicente Herrero-Bosch
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. ICSAMOS (2009)
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero
A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding. Microprocess. Microsystems 32 (1) (2008)
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona
A Mixed Hardware/Software SOFM Training System. Computación y Sistemas 11 (4) (2008)
Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, José María Monzó, Christoph W. Lerche, Jorge Daniel Martínez, Angel Sebastia, Fernando Mateo
SoC-Based Implementation of the Backpropagation Algorithm for MLP. HIS (2008)
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona
A wavelet-VQ system for real-time video compression. J. Real Time Image Process. 2 (4) (2007)
Fernando Mateo, Ramón José Aliaga, Jorge Daniel Martínez, José María Monzó, Rafael Gadea Gironés
Incidence Position Estimation in a PET Detector Using a Discretized Positioning Circuit and Neural Networks. IWANN (2007)
Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés
A Novel FPGA Architecture of a 2-D Wavelet Transform. J. VLSI Signal Process. 42 (3) (2006)
Joaquín Cerdá-Boluda, Marcos Martínez Peiró, Miguel A. Larrea Torres, Rafael Gadea Gironés, Ricardo José Colom-Palero
An active methodology for teaching electronic systems design. IEEE Trans. Educ. 49 (3) (2006)
Joaquín Cerdá, Rafael Gadea Gironés, Jorge Daniel Martínez, Angel Sebastia
A Tool for Implementing and Exploring SBM Models: Universal 1D Invertible Cellular Automata. IWINAC (1) (2005)
Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés
FPGA Implementation of a Pipelined On-Line Backpropagation. J. VLSI Signal Process. 40 (2) (2005)
Joaquín Cerdá-Boluda, Oscar Amoraga-Lechiguero, Ruben Torres-Curado, Rafael Gadea Gironés, Angel Sebastià-Cortés
FPGA Implementations of the RNR Cellular Automata to Model Electrostatic Field. VECPAR (2004)
Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocess. Microsystems 28 (9) (2004)
Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer
FPGA Custom DSP for ECG Signal Analysis and Compression. FPL (2004)
Joaquín Cerdá, Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastia
On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA. FPL (2003)
Rafael Gadea Gironés, Agustín Ramírez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero
FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. FPL (2003)
Joaquín Cerdá, Rafael Gadea Gironés, Guillermo Payá Vayá
Implementing a Margolus Neighborhood Cellular Automata on a FPGA. IWANN (2) (2003)
Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo
Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. ISSS (2000)
Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastia, Antonio Mocholí Salcedo
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks. FPL (2000)
Rafael Gadea Gironés, Antonio Mocholí Salcedo
Forward-Backward Parallelism in On-Line Backpropagation. IWANN (2) (1999)
Rafael Gadea Gironés, Antonio Mocholí Salcedo
Implementation with FPGAs of a pipelined on-line backpropagation. ICECS (1999)