Francisco José Ballester-Merelo

Publication Activity (10 Years)

Years Active: 2000-2021
Publications (10 Years): 3

Top Topics

Advanced Driver Assistance Systems

Vehicle Detection

Vlsi Architecture

Top Venues

Publications

Raúl Esteve Bosch, José F. Toledo Alarcón, Vicente Herrero-Bosch, Ander Simón Estévez, Francesc Monrabal Capilla, Vicente Álvarez Puerta, Javier Rodríguez Samaniego, Marc Querol Segura, Francisco José Ballester-Merelo
The Event Detection System in the NEXT-White Detector. Sensors 21 (2) (2021)
Nieves Gallego Ripoll, Luís Enrique Gómez Aguilera, Ferran Mocholí Belenguer, Antonio Mocholí Salcedo, Francisco José Ballester-Merelo
Design, Implementation, and Configuration of Laser Systems for Vehicle Detection and Classification in Real Time. Sensors 21 (6) (2021)
Melisa Acosta-Coll, Francisco José Ballester-Merelo, Marcos Martínez-Peiró, Emiro De la Hoz-Franco
Real-Time Early Warning System Design for Pluvial Flash Floods - A Review. Sensors 18 (7) (2018)
Armando Mora Campos, Francisco José Ballester-Merelo, Marcos Martínez Peiró, José A. Canals Esteve
Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management. Microprocess. Microsystems 32 (2) (2008)
Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá
2D-DCT on FPGA by polynomial transformation in two-dimensions. ISCAS (3) (2004)
Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocess. Microsystems 28 (9) (2004)
Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá
Architectures for ICT on FPGA. FPT (2004)
Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer
FPGA Custom DSP for ECG Signal Analysis and Compression. FPL (2004)
Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Vicente Herrero-Bosch, Joaquín Cerdá
A new inverse discrete wavelet packet transform architecture. ISSPA (2) (2003)
Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco Mora Campos
Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. FPL (2003)
Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo
Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. ISSS (2000)