Ricardo José Colom-Palero

Publication Activity (10 Years)

Years Active: 2003-2018
Publications (10 Years): 1

Top Topics

Optimization Method

Associative Memory

Highly Non Linear

Optimization Strategies

Top Venues

Publications

Rafael Gadea Gironés, Ricardo José Colom-Palero, Vicente Herrero-Bosch
Optimization of Deep Neural Networks Using SoCs with OpenCL. Sensors 18 (5) (2018)
Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá, Néstor Ferrando, Vicente Herrero-Bosch
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. ICSAMOS (2009)
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero
A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding. Microprocess. Microsystems 32 (1) (2008)
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona
A Mixed Hardware/Software SOFM Training System. Computación y Sistemas 11 (4) (2008)
Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, José María Monzó, Christoph W. Lerche, Jorge Daniel Martínez, Angel Sebastia, Fernando Mateo
SoC-Based Implementation of the Backpropagation Algorithm for MLP. HIS (2008)
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona
A wavelet-VQ system for real-time video compression. J. Real Time Image Process. 2 (4) (2007)
Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés
A Novel FPGA Architecture of a 2-D Wavelet Transform. J. VLSI Signal Process. 42 (3) (2006)
Joaquín Cerdá-Boluda, Marcos Martínez Peiró, Miguel A. Larrea Torres, Rafael Gadea Gironés, Ricardo José Colom-Palero
An active methodology for teaching electronic systems design. IEEE Trans. Educ. 49 (3) (2006)
Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés
FPGA Implementation of a Pipelined On-Line Backpropagation. J. VLSI Signal Process. 40 (2) (2005)
Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocess. Microsystems 28 (9) (2004)
Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer
FPGA Custom DSP for ECG Signal Analysis and Compression. FPL (2004)
Rafael Gadea Gironés, Agustín Ramírez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero
FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. FPL (2003)