Marcos Martínez Peiró

Publication Activity (10 Years)

Years Active: 2003-2008
Publications (10 Years): 0

Publications

Armando Mora Campos, Francisco José Ballester-Merelo, Marcos Martínez Peiró, José A. Canals Esteve
Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management. Microprocess. Microsystems 32 (2) (2008)
Joaquín Cerdá-Boluda, Marcos Martínez Peiró, Miguel A. Larrea Torres, Rafael Gadea Gironés, Ricardo José Colom-Palero
An active methodology for teaching electronic systems design. IEEE Trans. Educ. 49 (3) (2006)
Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá
2D-DCT on FPGA by polynomial transformation in two-dimensions. ISCAS (3) (2004)
Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocess. Microsystems 28 (9) (2004)
Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá
Architectures for ICT on FPGA. FPT (2004)
Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer
FPGA Custom DSP for ECG Signal Analysis and Compression. FPL (2004)
Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Vicente Herrero-Bosch, Joaquín Cerdá
A new inverse discrete wavelet packet transform architecture. ISSPA (2) (2003)
Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco Mora Campos
Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. FPL (2003)
Arturo Méndez Patiño, Marcos Martínez Peiró
2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions. VLSI-SOC (2003)