Panagiotis Merakos

Publication Activity (10 Years)

Years Active: 1996-2010
Publications (10 Years): 0

Publications

Michalis K. Tsiampas, Dimitrios Bountas, Panagiotis Merakos, Nestoras E. Evmorfopoulos, Sotiris Bantas, George I. Stamoulis
A power grid analysis and verification tool based on a Statistical Prediction Engine. ICECS (2010)
Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis, Nikos Haralabidis
A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-μm CMOS transceiver for 802.11a/b/g wireless LAN. IEEE J. Solid State Circuits 39 (7) (2004)
Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis, Constantinos E. Goutis
Power efficient data path synthesis of sum-of-products computations. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis, Nikos Haralabidis
A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18μm CMOS RF transceiver for 802.11a/b/g wireless LAN. ESSCIRC (2003)
Iason Vassiliou, Kostis Vavelidis, Theodore Georgantas, Sofoklis Plevridis, Nikos Haralabidis, George Kamoulakos, Charalambos Kapnistis, Spyros Kavadias, Yiannis Kokolakis, Panagiotis Merakos, Jacques C. Rudell, Akira Yamanaka, Stamatis Bouras, Ilias Bouras
A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN. IEEE J. Solid State Circuits 38 (12) (2003)
Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis
Power Efficient Vector Quantization Design Using Pixel Truncation. PATMOS (2002)
Konstantinos Masselos, Spyros Theoharis, Panagiotis Merakos, Thanos Stouraitis, Costas E. Goutis
Memory accesses reordering for interconnect power reduction in sum-of-products computations. IEEE Trans. Signal Process. 50 (11) (2002)
Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
Low power synthesis of sum-of-products computation (poster session). ISLPED (2000)
Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
Low power architectures for digital signal processing. J. Syst. Archit. 46 (7) (2000)
Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
Novel techniques for bus power consumption reduction in realizations of sum-of-product computation. IEEE Trans. Very Large Scale Integr. Syst. 7 (4) (1999)
Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
Computation Reordering: A Novel Transformation for Low Power DSP Synthesis. VLSI Design 1999 (2) (1999)
Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
Low power synthesis of sum-of-product computation in DSP algorithms. ISCAS (6) (1999)
Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
Trade-Off Analysis of a Low-Power Image Coding Algorithm. J. VLSI Signal Process. 18 (1) (1998)
Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
Low-power implementation of discrete wavelet transform. EUSIPCO (1998)
Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
A novel algorithm for low-power image and video coding. IEEE Trans. Circuits Syst. Video Technol. 8 (3) (1998)
Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Costas E. Goutis
Low-power image decoding using fractals. ICECS (1996)