Nobuaki Miyakawa

Publication Activity (10 Years)

Years Active: 1994-2014
Publications (10 Years): 0

Top Topics

Three Dimensional

Quantitative Analysis

Top Venues

Publications

Mostafa Said, Mohamed El-Sayed, Farhad Mehdipour, Nobuaki Miyakawa
Keep-Out-Zone analysis for three-dimensional ICs. VLSI-DAT (2014)
Nobuaki Miyakawa
A 3D prototyping chip based on a wafer-level stacking technology. ASP-DAC (2009)
Nobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda
Multilayer stacking technology using wafer-to-wafer stacked method. ACM J. Emerg. Technol. Comput. Syst. 4 (4) (2008)
Nobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda
Stacking technology based on 8-inch wafers using direct connection between TSV and micro-bump. CICC (2008)
Hajime Takashima, So Yamada, Shigeru Obara, Kunihiro Kitamura, Shinjiro Inabata, Nobuaki Miyakawa, Kazutoshi Tanabe, Umpei Nagashima
A novel parallel algorithm for large-scale Fock matrix construction with small locally distributed memory architectures: RT parallel algorithm. J. Comput. Chem. 23 (14) (2002)
Shinjiro Toyoda, Hiroh Miyagawa, Kunihiro Kitamura, Takashi Amisaki, Eiri Hashimoto, Hitoshi Ikeda, Akihiro Kusumi, Nobuaki Miyakawa
Development of MD Engine: High-speed accelerator with parallel processor design for molecular dynamics simulations. J. Comput. Chem. 20 (2) (1999)
Koji Hashimoto, Hiroto Tomita, Koji Inoue, Katsuhiko Metsugi, Kazuaki J. Murakami, Shinjiro Inabata, So Yamada, Nobuaki Miyakawa, Hajime Takashima, Kunihiro Kitamura, Shigeru Obara, Takashi Amisaki, Kazutoshi Tanabe, Umpei Nagashima
MOE: A Special-Purpose Parallel Computer for High-Speed, Large-Scale Molecular Orbital Calculation. SC (1999)
Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, Hikotaro Itani
Future system-on-silicon LSI chips. IEEE Micro 18 (4) (1998)
Tetsuro Kawata, Kenichi Kawauchi, Nobuaki Miyakawa, Ichiro Kawazome, Hiromi Yasumatsu, Susumu Haga, Masaya Takenaka
An outline font rendering processor with an embedded RISC CPU for high-speed hint processing. IEEE J. Solid State Circuits 29 (3) (1994)