Mateusz Majer

Publication Activity (10 Years)

Years Active: 2004-2008
Publications (10 Years): 0

University of Erlangen-Nuremberg (PHD)

Education History

University of Erlangen-Nuremberg

PHD

Publications

Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich
Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. IEEE International Workshop on Rapid System Prototyping (2008)
Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC (2008)
Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
Fine grain reconfigurable architectures. FPL (2008)
Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Trans. Very Large Scale Integr. Syst. 16 (9) (2008)
Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. J. VLSI Signal Process. 47 (1) (2007)
Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens). it Inf. Technol. 49 (3) (2007)
Mateusz Majer
An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization. FPL (2006)
Diana Göhringer, Mateusz Majer, Jürgen Teich
Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. Dynamically Reconfigurable Architectures (2006)
Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich
A Flexible Reconfiguration Manager for the Erlangen Slot Machine. ARCS Workshops (2006)
Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich
Minimizing Communication Cost for Reconfigurable Slot Modules. FPL (2006)
Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices CoRR (2005)
Christophe Bobda, Ali Ahmadinia, Kurapati Rajesham, Mateusz Majer, Adronis Niyonkuru
Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs. ARCS Workshops (2005)
Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich
The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. FPT (2005)
Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. FPL (2005)
Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich
Packet Routing in Dynamically Changing Networks on Chip. IPDPS (2005)
Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices CoRR (2005)
Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. IEEE International Workshop on Rapid System Prototyping (2005)
Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. FCCM (2005)
Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA (2005)
Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich
A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL (2004)
Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel
Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. MBMV (2004)
Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich
Task scheduling for heterogeneous reconfigurable computers. SBCCI (2004)
Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers (2004)

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Publication Activity (10 Years)

Mateusz Majer