Kjell O. Jeppson

Publication Activity (10 Years)

Years Active: 1987-2014
Publications (10 Years): 0

Top Topics

Learning Environment

Design Decisions

Top Venues

Publications

Per Larsson-Edefors, Kjell O. Jeppson
Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration. EWME (2014)
Kjell O. Jeppson, Per Larsson-Edefors
Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment. MSE (2013)
Kjell O. Jeppson
A learning tool MOSFET model: A stepping-stone from the square-law model to BSIM4. PATMOS (2013)
Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson
Noise Interaction Between Power Distribution Grids and Substrate. ISQED (2008)
Kjell O. Jeppson
A Student-Oriented Course in Digital VLSI Design. MSE (2007)
Rashid Farivar, Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson
Evaluation of using active circuitry for substrate noise suppression. ACM Great Lakes Symposium on VLSI (2007)
Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson
Properties and modeling of ground structures for reducing substrate noise coupling in ICs. ISCAS (2006)
Simon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Nebojsa Simic, Marinel Zgrda, Kjell O. Jeppson
A surface potential model for predicting substrate noise coupling in integrated circuits. IEEE J. Solid State Circuits 40 (9) (2005)
Simon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Kjell O. Jeppson
A surface potential model for predicting substrate noise coupling in integrated circuits. CICC (2004)
Kjell O. Jeppson
Comments on the metastable behavior of mismatched CMOS latches. IEEE J. Solid State Circuits 31 (2) (1996)
Nils Hedenstiema, Kjell O. Jeppson
Comments on the optimum CMOS tapered buffer problem. IEEE J. Solid State Circuits 29 (2) (1994)
Kjell O. Jeppson
Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay. IEEE J. Solid State Circuits 29 (6) (1994)
Nils Hedenstierna, Kjell O. Jeppson
The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (2) (1993)
Nils Hedenstierna, Kjell O. Jeppson
Comments on 'A module generator for optimized CMOS buffers'. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (1) (1993)
Kjell O. Jeppson, Sven Christensson, Nils Hedenstierna
Formal definitions of edge-based geometric design rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (1) (1993)
Nils Hedenstierna, Kjell O. Jeppson
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking. DAC (1989)
Nils Hedenstierna, Kjell O. Jeppson
The use of inverse layout trees for hierarchical design verification. ICCAD (1988)
Nils Hedenstierna, Kjell O. Jeppson
A corner-based hierarchical circuit extractor. Integr. 6 (3) (1988)
Nils Hedenstierna, Kjell O. Jeppson
New algorithms for increased efficiency in hierarchical design rule checking. Integr. 5 (3-4) (1987)
Nils Hedenstierna, Kjell O. Jeppson
CMOS Circuit Speed and Buffer Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (2) (1987)