Kisaburo Nakazawa

Publication Activity (10 Years)

Years Active: 1960-1999
Publications (10 Years): 0

Publications

Kisaburo Nakazawa, Hiroshi Nakamura, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
CP-PACS: A massively parallel processor at the University of Tsukuba. Parallel Comput. 25 (13-14) (1999)
Takayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku, Kisaburo Nakazawa
Advanced processor design using hardware description language AIDL. ASP-DAC (1997)
Taisuke Boku, Ken'ichi Itakura, Hiroshi Nakamura, Kisaburo Nakazawa
CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations. International Conference on Supercomputing (1997)
Taisuke Boku, Kisaburo Nakazawa, Hiroshi Nakamura, Takeshi Sone, Takeshi Mishima, Ken'ichi Itakura
Adaptive routing technique on hypercrossbar network and its evaluation. Systems and Computers in Japan 27 (4) (1996)
Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa
A superscalar RISC processor with pseudo vector processing feature. ICCD (1995)
Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. HICSS (1) (1994)
Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. International Conference on Supercomputing (1993)
Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe
Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline. SC (1992)
Kenro Murata, Kisaburo Nakazawa
Very high speed serial and serial-parallel computers HITAC 5020 and 5020E. AFIPS Fall Joint Computing Conference (1) (1964)
S. Takahashi, Kisaburo Nakazawa, Kenro Murata, Osamu Ishii
A Tunnel-Diode High-Speed Memory. IFIP Congress (1962)
Eiichi Goto, Kenro Murata, Kisaburo Nakazawa, Keisuke Nakagawa, Tohru Moto-Oka, Yasushi Miatsu-Oka, Yoshihiro Ishibashi, Haruhisa Ishida, Takashi Soma, Eiiti Wada
Esaki Diode High-Speed Logical Circuits. IRE Trans. Electron. Comput. 9 (1) (1960)