Hideo Wada

Publication Activity (10 Years)

Years Active: 1988-2013
Publications (10 Years): 0

Publications

Kiyoshi Nagata, Fidel R. Nemenzo, Hideo Wada
. Des. Codes Cryptogr. 67 (3) (2013)
Kiyoshi Nagata, Fidel R. Nemenzo, Hideo Wada
{Z_{p^3}}. Des. Codes Cryptogr. 50 (3) (2009)
Kiyoshi Nagata, Fidel R. Nemenzo, Hideo Wada
On Self-dual Codes over Z16. AAECC (2009)
Yoshiko Yasuda, Hiroaki Fujii, Hideya Akashi, Yasuhiro Inagami, Teruo Tanaka, Junji Nakagoshi, Hideo Wada, Tsutomu Sumimoto
Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201. IPPS (1997)
Hiroaki Fujii, Yoshiko Yasuda, Hideya Akashi, Yasuhiro Inagami, Makoto Koga, Osamu Ishihara, Masamori Kashiyama, Hideo Wada, Tsutomu Sumimoto
Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System. IPPS (1997)
Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. International Conference on Supercomputing (1993)
Hideo Wada, Tadaaki Isobe, Masao Furukawa, Shun Kawabe
High-speed storage control schemes of HITACHI supercomputer S-820 system. ICS (1989)
Michihiro Hirai, Shun Kawabe, Hideo Wada
An Overview of the HITACHI S-820 Supercomputer System. Supercomputer (1989)
Hideo Wada, K. Ishil, Masakazu Fukagawa, H. Murayama, Shun Kawabe
High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system. ICS (1988)
Hideo Wada, Koichi Ishii, Shigeko Yazawa, Shun Kawabe
High-Speed Vector Instruction Execution Schemes of HITACHI Supercomputer S-820 System. ICPP (1) (1988)