High-Speed Vector Instruction Execution Schemes of HITACHI Supercomputer S-820 System.

Hideo Wada Koichi Ishii Shigeko Yazawa Shun Kawabe

Published in: ICPP (1) (1988)

Keyphrases

high speed
low power
multimedia
high speed networks
building blocks
massively parallel
frame rate
execution model
sparse matrix
real time
vector data
data flow
vector space
fine grained
database
message passing
instructional design
floating point
database systems
neural network
learning disabled students