Khosrow Hajsadeghi

Publication Activity (10 Years)

Years Active: 2008-2020
Publications (10 Years): 8

Top Topics

Wide Dynamic Range

Cmos Technology

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Microelectron. J.

Publications

Saman Behrouzi, Zahra Shafaeipour Sarmoor, Khosrow Hajsadeghi, Kaveh Kavousi
Predicting scientific research trends based on link prediction in keyword networks. J. Informetrics 14 (4) (2020)
Hasan Molaei, Khosrow Hajsadeghi
A 5.3-ps, 8-b Time to Digital Converter Using a New Gain-Reconfigurable Time Amplifier. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Hasan Molaei, Khosrow Hajsadeghi, Ata Khorami
Design of low power comparator-reduced hybrid ADC. Microelectron. J. 79 (2018)
Hasan Molaei, Khosrow Hajsadeghi
A 1.6 ps 7 b time to digital converter in 0.18 µm CMOS technology. Microelectron. J. 67 (2017)
Hengameh Bahrami, Khosrow Hajsadeghi
Circuit design to improve security of telecommunication devices. CCWC (2017)
Hasan Molaei, Khosrow Hajsadeghi
A low-power comparator-reduced flash ADC using dynamic comparators. ICECS (2017)
Hasan Molaei, Khosrow Hajsadeghi
A low power high resolution time to digital converter for ADPLL application. MWSCAS (2016)
Hasan Molaei, Ata Khorami, Khosrow Hajsadeghi
A wide dynamic range low power 2× time amplifier using current subtraction scheme. ISCAS (2016)
Hasan Molaei, Ata Khorami, Mohammad S. Eslampanah Sendi, Khosrow Hajsadeghi
A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application. ICECS (2015)
Mohaddeseh Koosha, Khosrow Hajsadeghi, Mohammad Koosha
Fine logarithmic adaptive soft morphological algorithm for synthetic aperture radar image segmentation. IET Image Process. 8 (2) (2014)
Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi
Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Vahid Khojasteh Lazarjan, Khosrow Hajsadeghi
12 bits, 40MS/s, low power pipelined SAR ADC. MWSCAS (2014)
Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi
A Subthreshold Symmetric SRAM Cell With High Read Stability. IEEE Trans. Circuits Syst. II Express Briefs (1) (2014)
Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi, Roghayeh Saeidi
A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM. DTIS (2013)
Sina Hassanzadeh, Milad Zamani, Khosrow Hajsadeghi, Roghayeh Saeidi
A novel low power 8T-cell sub-threshold SRAM with improved read-SNM. DTIS (2013)
Mehdi Noormohammadi, Vahid Khojasteh Lazarjan, Khosrow Hajsadeghi
New Operational Transconductance Amplifiers using current boosting. MWSCAS (2012)
Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi
A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria. ISCAS (2011)
Amirehsan Behradfar, Saeed Zeinolabedinzadeh, Khosrow Hajsadeghi
A clock boosting scheme for low voltage circuits. ICECS (2008)