A low power high resolution time to digital converter for ADPLL application.
Hasan MolaeiKhosrow HajsadeghiPublished in: MWSCAS (2016)
Keyphrases
- low power
- high speed
- low cost
- power consumption
- high resolution
- mixed signal
- single chip
- vlsi architecture
- low power consumption
- application specific
- delay insensitive
- phase locked loop
- data conversion
- high power
- image processing
- digital signal processing
- user friendly
- vlsi circuits
- ultra low power
- power dissipation
- power reduction
- logic circuits
- cmos technology
- image sensor
- image compression
- video sequences