K. Gavaskar

Publication Activity (10 Years)

Years Active: 2019-2023
Publications (10 Years): 9

Top Topics

Low Power Consumption

Digital Signal Processing

Top Venues

Wirel. Pers. Commun.

J. Ambient Intell. Humaniz. Comput.

Publications

K. Gavaskar, P. Sivaranjani, S. Elango, G. Nirmal Raja
Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis. Wirel. Pers. Commun. 129 (1) (2023)
K. Gavaskar, U. S. Ragupathy
New approach for improving the performance of dual axis solar tracker with auto cleaning system. Soft Comput. 27 (24) (2023)
K. Gavaskar, D. Malathi, G. Ravivarma, P. S. Priyatharshan, S. Rajeshwari, B. Sanjay
Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors. Wirel. Pers. Commun. 128 (2) (2023)
K. Gavaskar, M. Sankara Narayanan, M. Sreenidhi Nachammal, K. Vignesh
Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay. J. Ambient Intell. Humaniz. Comput. 13 (9) (2022)
K. Gavaskar, D. Malathi, G. Ravivarma, V. Krithika Devi, M. Megala, S. Megaraj Begam
A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors. Wirel. Pers. Commun. 124 (2) (2022)
K. Gavaskar, D. Malathi, G. Ravivarma, V. Krithika Devi, M. Megala, S. Megaraj Begam
A Variant of Long Multiplication Design with Low Power and Area Using Modified 7: 3 Compressor for Biomedical Applications. Wirel. Pers. Commun. 127 (4) (2022)
K. Gavaskar, R. Dhivya, R. Dimple Dayana
Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies. Wirel. Pers. Commun. 125 (3) (2022)
K. Gavaskar, U. S. Ragupathy, V. Malini
Proposed Design of 1 KB Memory Array Structure for Cache Memories. Wirel. Pers. Commun. 109 (2) (2019)
K. Gavaskar, U. S. Ragupathy, V. Malini
Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories. Wirel. Pers. Commun. 108 (4) (2019)