Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies.
K. GavaskarR. DhivyaR. Dimple DayanaPublished in: Wirel. Pers. Commun. (2022)
Keyphrases
- low power
- single chip
- power consumption
- phase locked loop
- high speed
- low cost
- cmos technology
- vlsi architecture
- low power consumption
- logic circuits
- ultra low power
- power dissipation
- mixed signal
- vlsi circuits
- gate array
- nm technology
- cmos image sensor
- power reduction
- digital signal processing
- high power
- image sensor
- design process
- circuit design
- network traffic
- image processing
- delay insensitive
- multipath