Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors.
K. GavaskarD. MalathiG. RavivarmaP. S. PriyatharshanS. RajeshwariB. SanjayPublished in: Wirel. Pers. Commun. (2023)
Keyphrases
- low power
- logic circuits
- power dissipation
- power consumption
- low cost
- single chip
- high speed
- vlsi architecture
- low power consumption
- gate array
- power reduction
- digital signal processing
- parallel processing
- cmos technology
- design process
- wireless transmission
- long range
- parallel computing
- efficient implementation
- high power
- mixed signal
- ultra low power