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V. Malini
Publication Activity (10 Years)
Years Active: 2019-2019
Publications (10 Years): 2
Top Topics
Programmable Logic
Design Considerations
Dynamic Random Access Memory
High Speed
Top Venues
Wirel. Pers. Commun.
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Publications
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K. Gavaskar
,
U. S. Ragupathy
,
V. Malini
Proposed Design of 1 KB Memory Array Structure for Cache Memories.
Wirel. Pers. Commun.
109 (2) (2019)
K. Gavaskar
,
U. S. Ragupathy
,
V. Malini
Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories.
Wirel. Pers. Commun.
108 (4) (2019)