Jin-Fa Lin

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 10

Top Topics

Fpga Implementation

Matching Pursuit

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Bildverarbeitung für die Medizin

Publications

Jin-Fa Lin, Zheng-Jie Hong, Jun-Ting Wu, Xin-You Tung, Cheng-Hsueh Yang, Yu-Cheng Yen
Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design. Sensors 22 (15) (2022)
Zhi-Zhong Wang, Yi-Hsuan Hung, Jun-Ting Wu, Zheng-Jie Hong, Jin-Fa Lin
A 0.5V True-Single-Phase 16T Flip-Flop in 180-nm CMOS for IoT Applications. ICCE-TW (2021)
Ming-Hwa Sheu, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin, Jin-Fa Lin
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications. Sensors 21 (19) (2021)
Ching-Sheng Chang, Jin-Fa Lin, Ming-Ching Lee, Christoph Palm
Semantic Lung Segmentation Using Convolutional Neural Networks. Bildverarbeitung für die Medizin (2020)
Po-Yu Kuo, Chia-Hsin Hsieh, Jin-Fa Lin, Ming-Hwa Sheu, Yi-Ting Hung
Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design. IEICE Trans. Electron. (11) (2019)
Wei-Hsuan Ma, Kuan-Ying Chang, Kuan-Ting Chen, Yin-Tsung Hwang, Jin-Fa Lin
Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation. ISOCC (2019)
Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. ISCAS (2018)
Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Jin-Fa Lin, Ming-Yan Tsai, Kun-Sheng Li, Yun-Rong Jiang, Yu-Shiang Cheng
Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors. J. Low Power Electron. 12 (2) (2016)
Shin-Shiang Wang, Yi-Chi Tien, Yin-Tsung Hwang, Jin-Fa Lin, Guo-Zua Wu
MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging. APCCAS (2016)
Jin-Fa Lin
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Yin-Tsung Hwang, Jin-Fa Lin
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique. IEEE Trans. Very Large Scale Integr. Syst. 20 (9) (2012)
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
Low power 10-transistor full adder design based on degenerate pass transistor logic. ISCAS (2012)
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2010)
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
Low Power Pulse Generator Design Using Hybrid Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2010)
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu
Low Complexity Dual-Mode Pulse Generator Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2008)
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2007)
Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu
Low Power Multipliers Using Enhenced Row Bypassing Schemes. SiPS (2007)
Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. APCCAS (2006)
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho
A high speed and energy efficient full adder design using complementary & level restoring carry logic. ISCAS (2006)