Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.
Yin-Tsung HwangJin-Fa LinMing-Hwa SheuPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2012)
Keyphrases
- low power
- power dissipation
- power consumption
- cmos technology
- low cost
- single chip
- vlsi architecture
- flip flops
- high speed
- low power consumption
- logic circuits
- digital signal processing
- power reduction
- gate array
- design process
- wireless transmission
- mixed signal
- image sensor
- vlsi circuits
- digital circuits
- hardware and software
- high power
- low complexity
- image processing
- real time