Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.

Yin-Tsung Hwang Jin-Fa Lin Ming-Hwa Sheu Chia-Jen Sheu

Published in: APCCAS (2006)

Keyphrases

low power
power consumption
low cost
high speed
nm technology
vlsi architecture
single chip
high power
wireless transmission
low power consumption
digital signal processing
logic circuits
cmos technology
real time
power reduction
power dissipation
hardware and software
mixed signal