Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.
Jin-Fa LinMing-Hwa SheuYin-Tsung HwangChen-Syuan WongMing-Yan TsaiPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
- power dissipation
- low power
- flip flops
- logic circuits
- power consumption
- power reduction
- high speed
- cmos technology
- low cost
- digital signal processing
- single chip
- low power consumption
- single phase
- vlsi architecture
- nm technology
- gate array
- finite state machines
- delay insensitive
- ultra low power
- signal to noise ratio
- mixed signal