Low Power Multipliers Using Enhenced Row Bypassing Schemes.

Yin-Tsung Hwang Jin-Fa Lin Ming-Hwa Sheu Chia-Jen Sheu

Published in: SiPS (2007)

Keyphrases

low power
power consumption
low cost
high speed
high power
single chip
vlsi circuits
vlsi architecture
digital signal processing
logic circuits
low power consumption
power reduction
wireless transmission
mixed signal
gate array
general purpose
image sensor
message passing
digital camera