Hiroomi Hikawa

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 24

Top Topics

Asymptotic Stability

Majority Voting

Sign Recognition

Top Venues

IEEE Trans. Neural Networks Learn. Syst.

Publications

Takahiro Kawaguchi, Koki Ono, Hiroomi Hikawa
Electroencephalogram-Based Facial Gesture Recognition Using Self-Organizing Map. Sensors 24 (9) (2024)
Slavisa Jovanovic, Hiroomi Hikawa
A Survey of Hardware Self-Organizing Maps. IEEE Trans. Neural Networks Learn. Syst. 34 (11) (2023)
Yasuaki Kuroe, Seiji Miyoshi, Hiroomi Hikawa, Hidetaka Ito, Kimiko Motonaka, Yutaka Maeda
A Synthesis Method of Spiking Neural Oscillators with Considering Asymptotic Stability. IJCNN (2021)
Hiroomi Hikawa
Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (3) (2021)
Hiroomi Hikawa
Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors. ICECS (2020)
Hiroomi Hikawa
Nested Hardware Architecture for Self-Organizing Map. IJCNN (2019)
Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda
A New Hardware Self-Organizing Map Architecture with High Expandability. IPAS (2018)
Hiroomi Hikawa, Masayuki Tamaki, Hidetaka Ito
Off-Chip Training with Additive Perturbation for FPGA-Based Hand Sign Recognition System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2018)
Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda
A New Self-Organizing Map with Continuous Learning Capability. SSCI (2018)
Yuto Kurosaki, Masayoshi Ohta, Hidetaka Ito, Hiroomi Hikawa
SOM-Based Vector Recognition with Pre-Grouping Functionality. IEICE Trans. Inf. Syst. (6) (2018)
Hidetaka Ito, Hiroomi Hikawa, Yutaka Maeda
A Subspace Newton-Type Method for Approximating Transversely Repelling Chaotic Saddles. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Hiroomi Hikawa, Hidetaka Ito, Yutaka Maeda
Hardware Self-Organizing Map Based on Frequency-Modulated Signal and Digital Frequency-Locked Loop. ISCAS (2018)
Hiroomi Hikawa
Improved winner-take-all circuit for neural network based on frequency-modulated signals. ICECS (2016)
Masayoshi Ohta, Yuto Kurosaki, Hidetaka Ito, Hiroomi Hikawa
Effect of grouping in vector recognition system based on SOM. SSCI (2016)
Masayuki Tamaki, Hiroomi Hikawa
Live demonstration: Off-chip learning for hardware hand-sign recognition system. ISCAS (2016)
Masayuki Tamaki, Hiroomi Hikawa
Off-chip learning for hardware hand-sign recognition system. ISCAS (2016)
Yuta Ichikawa, Shuji Tashiro, Hidetaka Ito, Hiroomi Hikawa
Gesture Spotting by Using Vector Distance of Self-organizing Map. ICONIP (2) (2016)
Yuta Ichikawa, Shuji Tashiro, Hidetaka Ito, Hiroomi Hikawa
Real time gesture recognition system with gesture spotting function. SSCI (2016)
Hiroomi Hikawa
Vector classification by a winner-take-all neural network with digital frequency-locked loop. IJCNN (2015)
Hiroomi Hikawa
Winner-take-all neural network with digital frequency-locked loop. ISCAS (2015)
Katsuhiko Ueda, Zuiko Rikuhashi, Kentaro Hayashi, Hiroomi Hikawa
Low-Power Wiring Method for Band-Limited Signals in CMOS Logic Circuits by Segmentation Coding with Pseudo-Majority Voting. IEICE Trans. Electron. (4) (2015)
Hiroomi Hikawa, Yutaka Maeda
Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function. IEEE Trans. Neural Networks Learn. Syst. 26 (11) (2015)
Hiroomi Hikawa, Keishi Kaida
Novel FPGA Implementation of Hand Sign Recognition System With SOM-Hebb Classifier. IEEE Trans. Circuits Syst. Video Technol. 25 (1) (2015)
Masaki Azuma, Hiroomi Hikawa
Scalable Hardware Winner-Take-All Neural Network with DPLL. IEICE Trans. Inf. Syst. (10) (2015)
Masaki Azuma, Hiroomi Hikawa
Supervised learning of DPLL based winner-take-all neural network. ICES (2014)
Katsuhiko Ueda, Zuiko Rikuhashi, Kentaro Hayashi, Hiroomi Hikawa
Low-power wiring method in CMOS logics circuits by segmentation coding and pseudo majority voting. ISCAS (2014)
Masaki Azuma, Hiroomi Hikawa
A new winner-take-all neural network using DPLL and phase modulated signal. ISPACS (2013)
Naoki Terahara, Yoshiro Oba, Hiroomi Hikawa
Color-space image compression with hardware Self-organizing map. ISPACS (2013)
Hiroomi Hikawa
DPLL based hardware SOM with a new winner-take-all circuit. IJCNN (2013)
Yusuke Araga, Zuiko Rikuhashi, Hiroomi Hikawa
Sequential vector classifier based on SOM and feedback Hebbian network. ISPACS (2012)
Yusuke Araga, Makoto Shirabayashi, Keishi Kaida, Hiroomi Hikawa
Real time gesture recognition system using posture classifier and Jordan recurrent neural network. IJCNN (2012)
Hiroomi Hikawa
ROM-Less Phase to Amplitude Converter Using Sine Wave Approximation Based on Harmonic Removal from Trapezoid Wave. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2011)
Hiroomi Hikawa, Keishi Kaida
Hand sign recognition system based on SOM-Hebb hybrid network. SMC (2011)
Yutaka Maeda, Takahiro Yamada, Seiji Miyoshi, Hiroomi Hikawa
Learning Scheme for Complex Neural Networks Using Simultaneous Perturbation. ICANN (2) (2011)
Kota Yamamoto, Yoshiro Oba, Zuiko Rikuhashi, Hiroomi Hikawa
Automatic generation of hardware self-organizing map for FPGA implementation. ISPACS (2011)
Hiroomi Hikawa, Yusuke Araga
Study on gesture recognition system using posture classifier and Jordan recurrent neural network. IJCNN (2011)
Yoshiro Oba, Kota Yamamoto, Takahiro Nagai, Hiroomi Hikawa
Hardware design of a color quantization with self-organizing map. ISPACS (2011)
Hiroomi Hikawa, Kenji Doumoto, Simone Miyoshi, Yutaka Maeda
Image compression with hardware self-organizing map. IJCNN (2010)
Hiroomi Hikawa, Seito Yamazaki, Tatsuya Ando, Simone Miyoshi, Yutaka Maeda
Comparison of range check classifier and hybrid network classifier for hand sign recognition system. IJCNN (2010)
Hiroomi Hikawa, Taketo Namba
Phase amplitude converter with conditional shift operation. ISCAS (2010)
Hiroomi Hikawa
DDFS with New Sinusoid Approximation based on Harmonics Removal. ISCAS (2009)
Yuuki Taki, Hiroomi Hikawa, Seiji Miyoshi, Yutaka Maeda
Hand sign recognition system based on hybrid network classifier. IJCNN (2009)
Akira Onoo, Hiroomi Hikawa, Seiji Miyoshi, Yutaka Maeda
On automatic generation of VHDL code for self-organizing map. IJCNN (2009)
Seiji Miyoshi, Hiroomi Hikawa, Yutaka Maeda
Statistical Mechanical Analysis of Simultaneous Perturbation Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2009)
Yutaka Maeda, Naoto Matsushita, Seiji Miyoshi, Hiroomi Hikawa
On simultaneous perturbation particle swarm optimization. IEEE Congress on Evolutionary Computation (2009)
Hiroomi Hikawa, Hirotada Fujimura
Hardware Design of Japanese Hand Sign Recognition System. ICONIP (2) (2008)
Hirotada Fujimura, Yuuichi Sakai, Hiroomi Hikawa
Japanese Hand Sign Recognition System. ICONIP (1) (2007)
Hiroomi Hikawa, Taku Miyanishi, Kousuke Tamaya
Performance Comparison of SOM Based Hybrid Hardware Classifiers. IJCNN (2007)
Hiroomi Hikawa, Kazutoshi Harada, Takenori Hirabayashi
Hardware Feedback Self-Organizing Map and its Application to Mobile Robot Location Identification. J. Adv. Comput. Intell. Intell. Informatics 11 (8) (2007)
Hiroomi Hikawa, Kaori Kugimiya
A New Hardware Friendly Vector Distance Evaluation Function for Vector Classifiers. ICONIP (2) (2007)
Hiroomi Hikawa, Shigeki Matsubara
Pseudo RBF Network for Position Independent Hand Posture Recognition System. IJCNN (2007)
Hiroomi Hikawa
Vector Quantization System Based on Scalar SOM/AND-OR Hybrid Network. IJCNN (2006)
Shigeki Matsubara, Hiroomi Hikawa
Hardware friendly vector quantization algorithm. ISCAS (4) (2005)
Hiroomi Hikawa
FPGA implementation of self organizing map with digital phase locked loops. Neural Networks 18 (5-6) (2005)
Hiroomi Hikawa
Direct digital frequency synthesizer with multi-stage linear interpolation. ISCAS (4) (2004)
Hiroomi Hikawa
A new digital pulse-mode neuron with adjustable activation function. IEEE Trans. Neural Networks 14 (1) (2003)
Hiroomi Hikawa
A digital hardware pulse-mode neuron with piecewise linear activation function. IEEE Trans. Neural Networks 14 (5) (2003)
Hiroomi Hikawa
A multilayer neural network with pulse position modulation. Systems and Computers in Japan 34 (13) (2003)
Hiroomi Hikawa
Pulse mode neuron with leakage integrator and additive random noise. ISCAS (5) (2003)
Hiroomi Hikawa
Digital pulse mode neural network with simple synapse multiplier. ISCAS (3) (2001)
Hiroomi Hikawa
An efficient three-valued multilayer neural network with on-chip learning suitable for hardware implementation. Systems and Computers in Japan 31 (4) (2000)
Hiroomi Hikawa
Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning. IJCNN (2) (2000)
Hiroomi Hikawa
Pulse mode multilayer neural network based on floating point number representation. ISCAS (2000)
Kazuo Sato, Hiroomi Hikawa
Implementation of multilayer neural network with threshold neurons and its analysis. Artif. Life Robotics 3 (3) (1999)
Hiroomi Hikawa
An efficient pulse mode multilayer neural network. ISCAS (5) (1999)
Hiroomi Hikawa
Frequency-based multilayer neural network with on-chip learning and enhanced neuron characteristics. IEEE Trans. Neural Networks 10 (3) (1999)
Hiroomi Hikawa
Implementation of simplified multilayer neural networks with on-chip learning. ICNN (1995)
Vijay K. Jain, Hiroomi Hikawa
Parallel Architecture for Universal Digital Signal Processing. HICSS (1) (1994)
Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa
A radix-8 wafer scale FFT processor. J. VLSI Signal Process. 4 (2-3) (1992)
Vijay K. Jain, Hiroomi Hikawa, David C. Keezer
An Architecture for WSI Rapid Prototyping. Computer 25 (4) (1992)