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Low-power wiring method in CMOS logics circuits by segmentation coding and pseudo majority voting.
Katsuhiko Ueda
Zuiko Rikuhashi
Kentaro Hayashi
Hiroomi Hikawa
Published in:
ISCAS (2014)
Keyphrases
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low power
high speed
power consumption
low cost
segmentation method
vlsi circuits
neural network
segmentation algorithm
majority voting
power reduction
image segmentation
classification algorithm
data fusion
cmos technology
weighted voting
feature set
classification accuracy