A Novel Path Delay Fault Simulator Using Binary Logic.
Ananta K. MajhiJames JacobLalit M. PatnaikPublished in: VLSI Design (1996)
Keyphrases
- multi valued
- fault diagnosis
- fault detection
- logic programming
- shortest path
- logical operations
- test bed
- non binary
- path length
- predicate logic
- modal logic
- multiple faults
- logical framework
- real time embedded systems
- neural network
- fault model
- classical logic
- set theory
- asynchronous circuits
- proof theory
- automated reasoning
- optimal path
- destination node
- simulation model
- fault models
- expert systems