Low-power scan testing and test data compression forsystem-on-a-chip.
Anshuman ChandraKrishnendu ChakrabartyPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2002)
Keyphrases
- test data
- low power
- high speed
- low cost
- single chip
- test cases
- mixed signal
- cmos technology
- low power consumption
- power consumption
- image sensor
- power dissipation
- nm technology
- testing process
- search based testing
- signal processor
- training data
- ultra low power
- test set
- vlsi circuits
- image compression
- training set
- logic circuits
- power reduction
- data sets
- cmos image sensor
- compression algorithm
- software testing
- digital signal processing
- training and test data
- real time
- test data generation
- database
- gate array
- object oriented
- test suite
- vlsi implementation
- high density