An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs.
Pulkit JainJohn KeaneChris H. KimPublished in: ESSDERC (2012)
Keyphrases
- programmable logic
- chip design
- high density
- cmos technology
- silicon dioxide
- field effect transistors
- high speed
- image sensor
- real time
- gate dielectrics
- random access memory
- focal plane
- low cost
- neural network
- energy consumption
- nm technology
- analog vlsi
- life span
- single chip
- vlsi implementation
- data gathering
- low power
- signal processing
- content addressable memory