FPGA based hardware architecture for HIT/DLR hand.

R. Wei X. H. Gao Ming-He Jin Yiwei Liu Hong Liu Nikolaus Seitz Robin Gruber Gerd Hirzinger

Published in: IROS (2005)

Keyphrases

hardware architecture
hardware implementation
hardware architectures
field programmable gate array
associative memory
processing elements
neural network
pairwise
information systems
pattern recognition
artificial neural networks
scheduling problem
low cost
automated reasoning
block matching motion estimation