Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.
Bipul Chandra PaulCassondra NeauKaushik RoyPublished in: ITC (2004)
Keyphrases
- power dissipation
- analog vlsi
- high speed
- delay insensitive
- circuit design
- vlsi circuits
- power consumption
- cmos technology
- human body
- low power
- fault model
- fault diagnosis
- chip design
- fault detection
- random access memory
- atomic force microscopy
- focal plane
- logic circuits
- digital signal processing
- low cost
- failure modes
- expert systems
- fault models
- transmission line
- floating gate