Ziyad Hanna

Publication Activity (10 Years)

Years Active: 2001-2015
Publications (10 Years): 1

Top Venues

FMCAD

University of Oxford, UK (PHD)

Education History

University of Oxford, UK

PHD

Publications

Ziyad Hanna
Democratization of Formal Verification with Collective Intelligence. FMCAD (2015)
Ziyad Hanna
Challenging problems in industrial formal verification. FMCAD (2014)
Jamil Mazzawi, Ziyad Hanna
Formal Analysis of Security Data Paths in RTL Design. Haifa Verification Conference (2012)
Ziyad Hanna, Thomas F. Melham
A symbolic execution framework for algorithm-level modelling. HLDVT (2009)
Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability. ATS (2007)
Jacob Katz, Ziyad Hanna, Nachum Dershowitz
Space-Efficient Bounded Model Checking CoRR (2007)
Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver. SAT (2007)
Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. FMCAD (2007)
Ziyad Hanna
Abstract Modeling and Formal Verification of Microprocessors. CSR (2007)
Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Alberto Griggio, Ziyad Hanna, Alexander Nadel, Amit Palti, Roberto Sebastiani
A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems. CAV (2007)
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
Post-reboot Equivalence and Compositional Verification of Hardware. FMCAD (2006)
Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction CoRR (2006)
Marco Bozzano, Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Ziyad Hanna, Zurab Khasidashvili, Amit Palti, Roberto Sebastiani
Encoding RTL Constructs for MathSAT: a Preliminary Report. Electron. Notes Theor. Comput. Sci. 144 (2) (2006)
Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
Generation of shorter sequences for high resolution error diagnosis using sequential SAT. ASP-DAC (2006)
Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction. SAT (2006)
Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
A Clause-Based Heuristic for SAT Solvers. SAT (2005)
Nachum Dershowitz, Ziyad Hanna, Jacob Katz
Bounded Model Checking with QBF. SAT (2005)
Zurab Khasidashvili, Alexander Nadel, Amit Palti, Ziyad Hanna
Simultaneous SAT-Based Model Checking of Safety Properties. Haifa Verification Conference (2005)
Jacob Katz, Ziyad Hanna, Nachum Dershowitz
Space-Efficient Bounded Model Checking. DATE (2005)
Yulik Feldman, Nachum Dershowitz, Ziyad Hanna
Parallel Multithreaded Satisfiability Solver: Design and Implementation. Electron. Notes Theor. Comput. Sci. 128 (3) (2005)
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. ICCAD (2004)
Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna
A Signal Correlation Guided Circuit-SAT Solver. J. Univers. Comput. Sci. 10 (12) (2004)
Zurab Khasidashvili, Ziyad Hanna
SAT-based methods for sequential hardware equivalence verification without synchronization. Electron. Notes Theor. Comput. Sci. 89 (4) (2003)
Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
Design automation with mixtures of proof strategies for propositional logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (8) (2003)
Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. DAC (2003)
Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
A proof engine approach to solving combinational design automation problems. DAC (2002)
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
High capacity and automatic functional extraction tool for industrial VLSI circuit designs. ICCAD (2002)
Zurab Khasidashvili, John Moondanos, Ziyad Hanna
TRANS: efficient sequential verification of loop-free circuits. HLDVT (2002)
Amnon Rosenmann, Ziyad Hanna
Alignability equivalence of synchronous sequential circuits. HLDVT (2002)
John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV (2001)
Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna
An enhanced cut-points algorithm in formal equivalence verification. HLDVT (2001)

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Publication Activity (10 Years)

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Ziyad Hanna