John Moondanos

Publication Activity (10 Years)

Years Active: 1992-2018
Publications (10 Years): 1

Top Topics

Energy Dissipation

Top Venues

Publications

Michael K. Tsiampas, Nestor E. Evmorfopoulos, Konstantis Daloukas, John Moondanos, Georgios I. Stamoulis
A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine. DTIS (2018)
Nestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George I. Stamoulis, John Moondanos
Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis. ICCAD (2010)
Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability. ATS (2007)
John Moondanos
From Error to Error: Logic Debugging in the Many-Core Era. Electron. Notes Theor. Comput. Sci. 174 (4) (2007)
Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
Generation of shorter sequences for high resolution error diagnosis using sequential SAT. ASP-DAC (2006)
Abhijit Davare, Qi Zhu, John Moondanos, Alberto L. Sangiovanni-Vincentelli
JPEG Encoding on the Intel MXP5800: A Platform-Based Design Case Study. ESTIMedia (2005)
Maher N. Mneimneh, Karem A. Sakallah, John Moondanos
Preserving synchronizing sequences of sequential circuits after retiming. ASP-DAC (2004)
Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna
A Signal Correlation Guided Circuit-SAT Solver. J. Univers. Comput. Sci. 10 (12) (2004)
Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. DAC (2003)
Zurab Khasidashvili, John Moondanos, Ziyad Hanna
TRANS: efficient sequential verification of loop-free circuits. HLDVT (2002)
John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV (2001)
Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna
An enhanced cut-points algorithm in formal equivalence verification. HLDVT (2001)
Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos
Automatic verification of implementations of large circuits against HDL specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (3) (1997)
Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
Verification of Circuits Described in VHDL through Extraction of Design Intent. VLSI Design (1994)
Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
Abstraction of data path registers for multilevel verification of large circuits. Great Lakes Symposium on VLSI (1994)
John Moondanos, Jacob A. Abraham
Sequential Redundancy Identification Using Verification Techniques. ITC (1992)