Verification of Circuits Described in VHDL through Extraction of Design Intent.
Yatin Vasant HoskoteJohn MoondanosJacob A. AbrahamDonald S. FussellPublished in: VLSI Design (1994)
Keyphrases
- circuit design
- high speed
- hardware design
- engineering design
- digital circuits
- formal verification
- model checking
- software architecture
- hardware description language
- real time
- fpga implementation
- design decisions
- automatic extraction
- design process
- information extraction
- user interface
- face recognition
- information retrieval