Yeonbae Chung

Publication Activity (10 Years)

Years Active: 2000-2018
Publications (10 Years): 1

Top Topics

Random Access Memory

Logical Operations

Significantly Higher

Top Venues

IET Circuits Devices Syst.

Int. J. Circuit Theory Appl.

Publications

Sivasundar Manisankar, Yeonbae Chung
P-channel logic 2 T eDRAM macro with high retention bit architecture. Int. J. Circuit Theory Appl. 46 (7) (2018)
Weijie Cheng, Yeonbae Chung
Bit-area efficient embedded pseudo-SRAM utilising dual-threshold hybrid 2T gain cell. IET Circuits Devices Syst. 8 (2) (2014)
Weijie Cheng, Jeong-Wook Cho, Yeonbae Chung
Design of logic-compatible embedded DRAM using gain memory cell. ISOCC (2012)
Yeonbae Chung, Weijie Cheng
CMOS latch bit-cell array for low-power SRAM design. IEICE Electron. Express 7 (15) (2010)
Yeonbae Chung, Seung-Ho Song
Implementation of low-voltage static RAM with enhanced data stability and circuit speed. Microelectron. J. 40 (6) (2009)
Yeonbae Chung, Byung-Gil Jeon, Kang-Deog Suh
A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme. IEEE J. Solid State Circuits 35 (5) (2000)
Byung-Gil Jeon, Mun-Kyu Choi, Yoonjong Song, Seung-Kyu Oh, Yeonbae Chung, Kang-Deog Suh, Kinam Kim
A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit. IEEE J. Solid State Circuits 35 (11) (2000)