CMOS latch bit-cell array for low-power SRAM design.
Yeonbae ChungWeijie ChengPublished in: IEICE Electron. Express (2010)
Keyphrases
- low power
- power consumption
- single chip
- analog to digital converter
- low cost
- cmos technology
- high speed
- low power consumption
- vlsi architecture
- logic circuits
- nm technology
- power reduction
- mixed signal
- power dissipation
- image sensor
- digital signal processing
- ultra low power
- high power
- gate array
- wireless transmission
- power management
- vlsi circuits
- cmos image sensor
- power saving
- design process
- embedded systems
- signal processor