P-channel logic 2 T eDRAM macro with high retention bit architecture.

Sivasundar Manisankar Yeonbae Chung

Published in: Int. J. Circuit Theory Appl. (2018)

Keyphrases

long term
reasoning engine
wide range
modal logic
random access memory
design considerations
shift register
classical logic
logic programming
high speed
cognitive load
significantly higher
inference rules
multiple access
coding scheme
logical operations
flip flops