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Xueyi Yu
Publication Activity (10 Years)
Years Active: 2007-2020
Publications (10 Years): 1
Top Topics
Robust Tracking
Wiener Filter
Edge Enhancement
Noise Reduction
Top Venues
ISCAS
IEEE J. Solid State Circuits
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Publications
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Yanlong Zhang
,
Arindam Sanyal
,
Xueyi Yu
,
Xing Quan
,
Kailin Wen
,
Xiyuan Tang
,
Gang Jin
,
Li Geng
,
Nan Sun
PLL With Space-Time Averaging for Quantization Noise Reduction.
IEEE J. Solid State Circuits
55 (3) (2020)
Shuli Geng
,
Ni Xu
,
Jun Li
,
Xueyi Yu
,
Woogeun Rhee
,
Zhihua Wang
A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation.
ISCAS
(2013)
Yuanfeng Sun
,
Jian Qiao
,
Xueyi Yu
,
Woogeun Rhee
,
Byeong-Ha Park
,
Zhihua Wang
A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning.
IEEE Trans. Circuits Syst. I Regul. Pap.
(9) (2011)
Li Zhang
,
Xueyi Yu
,
Yuanfeng Sun
,
Woogeun Rhee
,
Dawn Wang
,
Zhihua Wang
,
Hongyi Chen
A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops.
IEEE J. Solid State Circuits
44 (11) (2009)
Xueyi Yu
,
Woogeun Rhee
,
Zhihua Wang
,
Jung-Bae Lee
,
Changhyun Kim
A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation.
ISSCC
(2009)
Jian Qiao
,
Xueyi Yu
,
Woogeun Rhee
,
Zhihua Wang
Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL.
ISCAS
(2009)
Xueyi Yu
,
Yuanfeng Sun
,
Woogeun Rhee
,
Hyung Ki Ahn
,
Byeong-Ha Park
,
Zhihua Wang
A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications.
IEEE J. Solid State Circuits
44 (8) (2009)
Xueyi Yu
,
Yuanfeng Sun
,
Woogeun Rhee
,
Zhihua Wang
An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators.
IEEE J. Solid State Circuits
44 (9) (2009)
Xueyi Yu
,
Yuanfeng Sun
,
Li Zhang
,
Woogeun Rhee
,
Zhihua Wang
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering.
ISSCC
(2008)
Xueyi Yu
,
Yuanfeng Sun
,
Woogeun Rhee
,
Zhihua Wang
,
Hyung Ki Ahn
,
Byeong-Ha Park
A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications.
CICC
(2008)
Baoyong Chi
,
Xueyi Yu
,
Woogeun Rhee
,
Zhihua Wang
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider.
ISCAS
(2007)